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MICROPOWER PHASE LOCKED LOOP
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VCO Section input signals on which the PLL will lock if it was. The VCO requires one external capacitor C1 and initially out of lock is defined as the frequency. one or two external resistors R1 or R1 and R2 capture range 2 fC The frequency range of input. Resistor R1 and capacitor C1 determine the signals on which the loop will stay locked if it was. frequency range of the VCO and resistor R2 initially in lock is defined as the frequency lock. enables the VCO to have a frequency offset if range 2 fL The capture range is the lock range. required The high input impedance 1012 of the With phase comparator I the range of frequencies. VCO simplifiers the design of low pass filters by over which the PLL can acquire lock capture. permitting the designer a wide choice of range is dependent on the low pass filter. resistor to capacitor ratios In order not to load the characteristics and can be made as large as the. low pass filter a source follower output of the lock range Phase comparator I enables a PLL. VCO input voltage is provided at terminal 10 system to remain in lock in spite of high amounts. DEMODULATED OUTPUT If this terminal is of noise in the input signal One characteristic of. used a load resistor RS of 10 K or more should this type of phase comparator is that it may lock. be connected from this terminal to VSS If unused onto input frequencies that are close to harmonics. this terminal should be left open The VCO can be of the VCO center frequency A second. connected either directly or through frequency characteristic is that the phase angle between the. dividers to the comparator input of the phase signal and the comparator input varies between 0. comparators A full CMOS logic swing is available and 180 and is 90 at the center frequency Fig 1. at the output of the VCO and allows direct shows the typical triangular phase to output. coupling to CMOS frequency dividers such as the response characteristic of phase comparator I. HCF4024B HCF4018B HCF4020B HCF4022B Typical waveforms for a CMOS. HCF4029B and HBF4059A One or more phase locked loop employing phase comparator I. HCF4018B Presettable Divide by N Counter or in locked condition of fo is shown in fig 2. HCF4029B Presettable Up Down Counter or Phase comparator II is an edge controlled digital. HBF4059A Programmable Divide by N memory network It consists of four flip flop. Counter together with the HCF4046B stages control gating and a three stage. Phase Locked Loop can be used to build a output circuit comprising p and n type drivers. micropower low frequency synthesizer A logic 0 having a common output node When the p MOS. on the INHIBIT input enables the VCO and the or n MOS drivers are ON they pull the output up to. source follower while a logic 1 turns off both to VDD or down to VSS respectively This type of. minimize stand by power consumption phase comparator acts only on the positive edges. of the signal and comparator inputs The duty, Phase Comparators cycles of the signal and comparator inputs are not. The phase comparator signal input terminal 14 important since positive transitions control the PLL. can be direct coupled provided the signal swing is system utilizing this type of comparator If the. within CMOS logic levels logic 0 30 of signal input frequency is higher than the. VDD VSS logic 1 70 of V DD VSS For comparator input frequency the p type output. smaller swings the signal must be capacitively driver is maintained ON most of the time and both. coupled to the self biasing amplifier at the signal the n and p drivers OFF 3 state the remainder of. input Phase comparator I is an exclusive OR the time If the signal input frequency is lower than. network it operates analagously to an over driven the comparator input frequency the n type output. balanced mixer To maximize the lock range the driver is maintained ON most of the time and both. signal and comparator input frequencies must the n and p drivers OFF 3 state the remainder of. have a 50 duty cycle With no signal or noise on the time If the signal and comparator input. the signal input this phase comparator has an frequencies are the same but the signal input lags. average output voltage equal to VDD 2 The the comparator input in phase the n type output. low pass filter connected to the output of phase driver is maintained ON for a time corresponding. comparator I supplies the averaged voltage to the to the phase difference If the signal and. VCO input and causes the VCO to oscillate at the comparator input frequencies are the same but. center frequency fo The frequency range of the comparator input lags the signal in phase the. p type output driver is maintained ON for a time signal and comparator input over the full VCO. corresponding to the phase difference frequency range Moreover the power dissipation. Subsequently the capacitor voltage of the due to the low pass filter is reduced when this type. low pass filter connected to this phase comparator of phase comparator is used because both the p. is adjusted until the signal and comparator inputs and n type output drivers are OFF for most of the. are equal in both phase and frequency At this signal input cycle It should be noted that the PLL. stable point both p and n type output drivers,lock range for this type of phase comparator is. remain OFF and thus the phase comparator, output becomes an open circuit and holds the equal to the capture range independent of the. voltage on the capacitor of the low pass filter low pass filter With no signal present at the signal. constant Moreover the signal at the phase input the VCO is adjusted to its lowest frequency. pulses output is a high level which can be used for phase comparator II Fig 3 shows typical. for indicating a locked condition Thus for phase waveforms for a CMOS PLL employing phase. comparator II no phase difference exists between comparator II in a locked condition. Figure 1 Phase Comparator I Characteristics at Low Pass Filter Output. Figure 2 Typical Waveforms for CMOS Phase Locked Loop Employing Phase Comparator I in Locked. Condition of fo, Figure 3 Typical Waveforms for CMOS Phase locked Loop Employing Phase Comparator II In Locked. INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION,PIN No SYMBOL NAME AND FUNCTION.
1 PHASE PULSES Phase Comparator,Pulse Output,2 PHASE COMP I Phase Comparator 1. OUT Output,3 COMPARATOR IN Comparator Input,4 VCO OUT VCO Output. 5 INHIBIT Inhibit Input,6 7 C1 Capacitors,9 VCO IN VCO Input. 10 DEMODULATOR Demodulator Output,11 R1 TO VSS Resistor R1 Connection. 12 R2 TO VSS Resistor R2Connection,13 PHASE COMP II Phase Comparator 2.
OUT Output,14 SIGNAL IN Signal Input,15 ZENER Diode Zener. 8 VSS Negative Supply,16 VDD Positive Supply Voltage. FUNCTIONAL DIAGRAM,ABSOLUTE MAXIMUM RATINGS,Symbol Parameter Value Unit. VDD Supply Voltage 0 5 to 22 V,VI DC Input Voltage 0 5 to VDD 0 5 V. II DC Input Current 10 mA,PD Power Dissipation per Package 200 mW.
Power Dissipation per Output Transistor 100 mW,Top Operating Temperature 55 to 125 C. Tstg Storage Temperature 65 to 150 C, Absolute Maximum Ratings are those values beyond which damage to the device may occur Functional operation under these conditions is. not implied, All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS,Symbol Parameter Value Unit. VDD Supply Voltage 3 to 20 V,VI Input Voltage 0 to VDD V.
Top Operating Temperature 55 to 125 C,DC SPECIFICATIONS. Test Condition Value, Symbol Parameter TA 25 C 40 to 85 C 55 to 125 C Unit. VI VO IO VDD,Min Typ Max Min Max Min Max,VCO SECTION. VOH High Level Output 0 5 1 5 4 95 4 95 4 95,Voltage 0 10 1 10 9 95 9 95 9 95 V. 0 15 1 15 14 95 14 95 14 95,VOL Low Level Output 5 0 1 5 0 05 0 05 0 05.
Voltage 10 0 1 10 0 05 0 05 0 05 V,15 0 1 15 0 05 0 05 0 05. IOH Output Drive 0 5 2 5 1 5 1 36 3 2 1 15 1 1,Current 0 5 4 6 1 5 0 44 1 0 36 0 36. 0 10 9 5 1 10 1 1 2 6 0 9 0 9,0 15 13 5 1 15 3 0 6 8 2 4 2 4. IOL Output Sink 0 5 0 4 1 5 0 44 1 0 36 0 36,Current 0 10 0 5 1 10 1 1 2 6 0 9 0 9 mA. 0 15 1 5 1 15 3 0 6 8 2 4 2 4,Input Leakage,0 18 Any Input 18 10 5 0 1 1 1 A.
PHASE COMPARATOR SECTION,IDD Total Device 0 5 5 0 05 0 1 0 1 0 1. Current 0 10 10 0 25 0 5 0 5 0 5,Pin 14 Open mA,0 15 15 0 75 1 5 1 5 1 5. 0 20 20 2 4 4 4,Total Device 0 5 5 0 04 5 150 150,Current 0 10 10 0 04 10 300 300. Pin 14 VSS or VDD A,0 15 15 0 04 20 600 600,0 20 20 0 08 100 3000. IOH Output Drive 0 5 2 5 1 5 1 36 3 2 1 15 1 1,Current 0 5 4 6 1 5 0 44 1 0 36 0 36.
0 10 9 5 1 10 1 1 2 6 0 9 0 9,0 15 13 5 1 15 3 0 6 8 2 4 2 4. IOL Output Sink 0 5 0 4 1 5 0 44 1 0 36 0 36,Current 0 10 0 5 1 10 1 1 2 6 0 9 0 9 mA. 0 15 1 5 1 15 3 0 6 8 2 4 2 4,VIH High Level Input 0 5 4 5 1 5 3 5 3 5 3 5. Voltage 1 9 1 10 7 7 7 V,1 5 13 5 1 15 11 11 11,VIL Low Level Input 4 5 0 5 1 5 1 5 1 5 1 5. Voltage 9 1 1 10 3 3 3 V,13 5 1 5 1 15 4 4 4,II Input Leakage.
0 18 Any Input 18 10 5 0 1 1 1 A,IOUT High Impedance. 0 18 Any Input 18 10 4 0 4 12 12 A,Leakage Current. CI Input Capacitance Any Input 5 7 5 pF, The Noise Margin for both 1 and 0 level is 1V min with VDD 5V 2V min with VDD 10V 2 5V min with VDD 15V. ELECTRICAL CHARACTERISTICS Tamb 25 C,Test Condition Value. Symbol Parameter Unit,VDD V Min Typ Max,VCO SECTION.
PD Operating Power 5 fO 10KHz R1 10M 70 140,Dissipation 10 R2 VCOIN VDD 2 800 1600 W. 15 3000 6000,fMAX Maximum 5 R1 10K C1 50pF 0 3 0 6. frequency 10 R2 VCOIN VDD 0 6 1 2 ns,15 0 8 1 6,5 R1 5K C1 50pF 0 5 0 8. 10 R2 VCOIN VDD 1 1 4 ns,15 1 4 2 4, Center Frequency Programable with external components R1 R2 and C1. fO and frequency,Range fmax fmin See Design Information.
Linearity 5 0 3 1 7,VCOIN 2 5V R1 10K,10 VCOIN 5V 1 R1 100K 0 5. 10 VCOIN 5V 2 5 R1 400K 4,15 VCOIN 7 5V 1 5 R1 100K 0 5. 15 VCOIN 7 5V 5 R1 1M 7,Temperature 5 0 12,Frequency Stability 10 0 04. no frequency,offset fmin 0 15 0 015,Temperature 5 0 09. Frequency Stability 10 0 07,frequency offset,fmin 0 15 0 03.
VCO Output Duty Cycle 5 10 15 50,tTLH tTHL VCO Output 5 100 200. Transition Time 10 50 100 ns,Source Follower Out 5 10 15 RS 10K 1 8 2 5 V. put Demodulated,Output Offset Volt,age VCOIN VDEM,Source Follower 5 RS 100K VCOIN 2 5V 0 3 0 3. Output Demodulated,Output Linearity 10 RS 300K VCOIN 5V 2 5 0 7. 15 RS 500K VCOIN 7 5V 5 0 9,VZ Zener Diode Volt IZ 50 A 4 45 5 5 7 5 V.
Zener Dynamic IZ 1 mA 40,Resistance,Test Condition Value. Symbol Parameter Unit,VDD V Min Typ Max,PHASE COMPARATOR SECTION. R14 Pin 14 signal in 5 1 2,Input Resistance 10 0 2 0 4 M. 15 0 1 0 2,AC Coupled Signal 5 fIN 100KHz sine wave 180 360. Input Sensivity 10 330 660 mV,peak to peak,15 900 1800.
tPLH Propagation Delay 5 225 450,Time High to Low 10 100 200 ns. Level Pins 14 to 1,tPLH Propagation Delay 5 350 700. Time Low to High 10 150 300 ns,15 100 200,tPHZ Disable Time High 5 225 450. Level to High 10 100 200 ns,Pins 14 to 13 15 65 130. tPLZ Disable Time Low 5 285 570,Level to High 10 130 260 ns.
tr tf Input Rise or Fall 5 50,Time Comparator 10 1 s. Signal Pin 14 5 500,tTLH tTHL Transition Time 5 100 200. 10 50 100 ns, For sine Wave the frequency must be greater than 10KHz for Phase Comparator II. DESIGN INFORMATION This information is a guide for approximating the value of external components. in a Phase Locked Loop system The selected external components must be within the following ranges. 5K R 1 R2 R S 1M C 1 100pF at VDD 5V C1 50pF at VDD 10V. USING PHASE COMPARATOR I USING PHASE COMPARATOR II. CHARACTERISTICS VCO WITHOUT VCO WITH VCO WITHOUT VCO WITH. OFFSET R2 OFFSET OFFSET R2 OFFSET,VCO Frequency, VCO in PLL System will Adjust to Centre VCO in PLL System will Adjust to Lowest. For No Signal Input,Frequency fo Operating Frequency fo.
Frequency Lock Range 2 fL Full VCO Frequency Range. 2fL 2fL fmax fmin,Frequency Lock Range,Loop filter Component. Phase Angle Between 90 at Centre frequency fO approximating. Always 0 in lock, SIgnal and Comparator 0 and 180 at ends of lock range 2 fL. Locks on Harmonics of,Centre Frequency,Signal Input Nose Rejec. For further information see, 1 F Gardner Phase Lock Techniques John Wiley and Sons New York 1966. 2 G S Mosckytz miniaturized RC filters using phase Lockedloop BSTJ May 1965. Plastic DIP 16 0 25 MECHANICAL DATA,MIN TYP MAX MIN TYP MAX.
a1 0 51 0 020,B 0 77 1 65 0 030 0 065,b 0 5 0 020,b1 0 25 0 010. D 20 0 787,E 8 5 0 335,e 2 54 0 100,e3 17 78 0 700. F 7 1 0 280,I 5 1 0 201,L 3 3 0 130,Z 1 27 0 050,SO 16 MECHANICAL DATA. MIN TYP MAX MIN TYP MAX,A 1 75 0 068,a1 0 1 0 2 0 003 0 007. a2 1 65 0 064,b 0 35 0 46 0 013 0 018,b1 0 19 0 25 0 007 0 010.
C 0 5 0 019,D 9 8 10 0 385 0 393,E 5 8 6 2 0 228 0 244. e 1 27 0 050,e3 8 89 0 350,F 3 8 4 0 0 149 0 157,G 4 6 5 3 0 181 0 208. L 0 5 1 27 0 019 0 050,M 0 62 0 024, Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the. consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from. its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications. mentioned in this publication are subject to change without notice This publication supersedes and replaces all information. previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or. systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 2001 STMicroelectronics Printed in Italy All Rights Reserved. STMicroelectronics GROUP OF COMPANIES, Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco. Singapore Spain Sweden Switzerland United Kingdom,http www st com.

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