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DESIGN OF HIGH SPEED MULTIPLIER USING BICMOS LOGIC FOR
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International Journal of Scientific Engineering Research Volume 4 Issue 6 June 2013 2829. ISSN 2229 5518, 3 LATCHUP PROBLEM IN CMOS performance so it is better technique to add both process in. substrate and finally BICMOS structure arises in single. substrate shown in fig 3 below But one disadvantage is. Latch up is a state where a semiconductor device undergoes a. Complexity and scalability of manufacture process are major. high current state as a result of interaction between a pnp and. challenges of BiCMOS circuits , an npn bipolar transistor The pnp and npn transistors can be. natural to the technology or parasitic devices In CMOS. technology these are typically parasitic devices For each p . channel MOSFET metal oxide semiconductor field effect. transistor device there is a corresponding parasitic pnp. element formed between the p channel diffusion the n well. and the substrate For each n channel MOSFET NMOS , device there is a corresponding parasitic NPN element. formed between the n channel diffusion the p substrate and. the n well of the p channel MOSFET For each inverter gate . there are corresponding pnp and npn parasitic bipolar. elements Fig 2 shows an example of a cross section of a Fig 3 BICMOS structure. CMOS inverter circuit , 5 BICMOS LOGIC STYLES, BiCMOS inverter circuit is shown in Fig 3 When VIN is. equal to zero then M1 transistor is turn ON then both M2 and. M3 transistors are OFF Turn ON the M1 and turn OFF the. M3 provide Q1 base Current and turn it ON In the other side. IJSER, turning OFF the M2 makes no current reaches to Q2 Base at.
the same time the M4 can discharge the electron charges in. the Q2 base in a very short time , Fig 2 Basic CMOS Inverter Cross Section with Latch Up. Circuit Model, When interaction occurs between a pnp and an npn bipolar. transistor regenerative feedback between the two transistors. can lead to electrical instability This interaction between a. three region PNP and a three region npn that share base and. collector regions can be viewed as a four region pnpn device. 1 3 As a result of the feedback between the two transistors . there exist stable and unstable regions in the I V. characteristic When these parasitic pnpn elements undergo a. high current state latch up can initiate thermal runaway and. can be destructive 4 Latch up events can lead to destruction. Fig 4 Schematic diagram of conventional BiCMOS, of a semiconductor chip package or system This latch up. inverter,problem is minimized by BICMOS structure . Therefore great current IEQ1 completely charge Cload. 4 MINIMIZATION OF LATCHUP IN, capacitor The gate delay propagation from low to high.
BICMOS voltage will be low When Vin is equal to Vcc the M is turn. OFF then both M2 and M3 are on Turning ON the M3 makes. How latch up is minimized by BICMOS structure It can be the voltage Gate of M4 being equal to zero therefore it will be. done by adding retrograde n well and epitaxial layer in an OFF High voltage of Vout and turning ON the M2 then. substrate As far as MOSFET performance is concerned with turning OFF the M4 supply the current base of the Q2 and. low doping substrate to achieve efficient performance But by turn it ON Finally Cload capacitor via the Q2 transistor and. increasing doping concentration only latch up problem is great current ICQ2 can be discharged quickly Simliarly the. minimized So without degrading the MOSFET performance and or and xor BICMOS logics are shown below in figures. a heavily doped n well will be fabricated underneath the low 5 6 and 7 . doped n well by ion implantation this process is known as. retrograde n well and it also eliminates the subsurface punch. through which normally occurs in low doped well Similarly. by adding epitaxial layer it provide optimal MOSFET. IJSER 2013, http www ijser org, International Journal of Scientific Engineering Research Volume 4 Issue 6 June 2013 2830. ISSN 2229 5518, carry from the less significant previous adder The number of. rows in array multiplier denotes length of the multiplier and. width of each row denotes width of multiplicand The output. of each row of adders acts as input to the next row of adders . Each row of full adders or 3 2 compressors adds a partial. product to the partial sum generating a new partial sum and a. sequence of carries as shown in Fig 14 Schematic diagram of. unsigned Array Multiplier is shown in Fig 15 In this figure. a3 a2 a1 a0 is multiplicand and b3 b2 b1 b0 is, multiplier In place of input bit pattern voltage source is. applied P7P6P5P4P3P2P1P0 is the output of multiplier where. P0 is LSB and P7 is MSB, Fig 5 BICMOS AND logic, IJSER. Fig 8 Schematic diagram of 4 4 unsigned Array, multiplier architecture.
Fig 6 BICMOS OR logic, Fig 7 BICMOS XOR logic,6 MULTIPLIER ARCHITECTURE. The multipliers play a major role in arithmetic operations in. digital signal processing DSP applications The present. development in processor designs aim at design of low power. multiplier So the need for low power multipliers has. increased Generally the computational performance of DSP. processors is affected by its multipliers performance In this. Fig 8 a 4 4 unsigned Array multiplier architecture using. section we design 4 bit unsigned Array multiplier . BICMOS in cadence, An Array multiplier 14 is very regular in structure An n bit. Array multiplier has n x n array of AND gates to generate The delay associated with the array multiplier is the time. partial products n x n 2 full adders and n half adders Each taken by the signals to propagate through the AND gates and. partial product bit is fed into a full adder which sums the adders that form the multiplication array Delay of an array. partial product bit with the sum from the previous adder and a multiplier depends only upon the depth of the array not on the. IJSER 2013, http www ijser org, International Journal of Scientific Engineering Research Volume 4 Issue 6 June 2013 2831. ISSN 2229 5518, partial product width The delay of the array multiplier is. given by 15 , T critical N 1 N 2 T carry N 1 T Sum T.
AND 3 , Where T carry is the propagation delay between input and. output carry T Sum is the delay between the input carry and. sum bit of the full adder T AND is the delay of AND gate N. is the length of multiplier operand The advantage of array. multiplier is its regular structure Therefore it is easy to layout. and has small size In VLSI designs the regular structures can. be cemented over one another This reduces the risk of Fig 9 Contd Simulated waveform for 4 4 unsigned. mistakes and also reduces layout design time This regular Array multiplier. layout is widely used in VLSI math co processors and DSP. Table 1 Delay comparison between CMOS BICMOS,chips 16 . ARRAY DELAY ns ,7 SIMULATION RESULTS AND MULTIPLIER. ANALYSIS CMOS BICMOS, Cadence Spectre Simulator simulates the design using with 2 2 16 37 21 6. 180nm technology for BICMOS array multiplier Simulation. results are shown that a proposed BICMOS have better 4 4 7 888 6 388. performance in terms of delay than the CMOS The simulated. IJSER, waveform and its delay value is shown in fig 9 table 1.
8 CONCLUSION, It has been observed that BICMOS logic exhibit better. characteristics as compared to CMOS when we consider large. load So BICMOS can be used where high speed is the prime. aim Design strategies for multiplier employing BiCMOS. technology shown that low voltage low power and high. speed application is possible , 9 REFERENCES, 1 Sung mo kang Yusuf Leblebici CMOS digital. Integrated circuit s analysis and design Tata Mc Graw hill. Third edition 2008 , 2 Kiat seng yeo kaushik Roy Low voltage Low power VLSI. Subsystems Tata McGraw Hill edition 2009 , 3 Douglas A Pucknell Basic of VLSI design Prentice Hall . Inc 2007 , 4 K Ueda H Suzuki K Suda H Shinohara and K Mashiko .
A 64 bit carry look ahead adder using pass transistor. BiCMOS gates IEEE Journal of Solid State Circuits . 5 C Chen 2 5 V Bipolar CMOS Circuits for 0 25 mm, BICMOS Technology IEEE Journal of Solid State Circuits . vol 27 no 4 April 1992 , 6 C T Chuang Advanced Bipolar Circuits IEEE Circuits. and Systems Magazine pp 32 36 November 1992 , 7 D Chen and C Zukowski CMOS optimization including. logic family mixing in Proc IEEE Int Symp Circuits and. Systems 1991 pp 2240 2243 , 8 P Duchene and M Declercq Strategies for CMOS Bicmos. gate usage on sea of gates arrays in Proc IEEE 1991. Custom Integrated Circuits Conf 1991 pp 14 2 1 14 2 4. 9 L Wissel and E Gould Optimal usage of CMOS within a. Bicmos technology IEEE J Solid State Circuits vol 27 . pp 300 306 Mar 1992 , 10 J H LOU and J B KUO A 1 5 V Fd Swing.
Fig 9 Simulated waveform for 4 4 unsigned Array bootStEIpped CMOS Large Capacitiv Load Driver Circuit. Suitable for Low Voltage CMOS VLSI J SoZidslote, multiplier Cirruils IEEE vol 32 no l pp 119 121 Jan 1997 . 11 P C Chen and J B Kuo SublV CMOS Large, IJSER 2013. http www ijser org, International Journal of Scientific Engineering Research Volume 4 Issue 6 June 2013 2832. ISSN 2229 5518, Capacitive had Driver Circuit Using Direct Bootstrap monolithic integrated resistive mixers with low distortion. Technique for Low Voltage CMOS VLSI Electronics for HIPERLAN IEEE Transactions on Microwave. Letfers IEE vol 38 no 6 pp 245 266 March 2002 Theory Technology vol 50 Jan 2002 pp 178 182 . 12 C I H Chen and A Kumar Area time optimal digital 14 S H K Embabi A Bellaouar M I Elmasry and R A . BiCMOS carry lookahead adder IEEE Asia Pacific Hadaway New fullvoltage swing BiCMOS buffers . Conference on Circuits and Systems APCCAS 94 Dec IEEE Journal of Solid State Circuits vol 26 no 2 Feb . 5 8 1994 pp 115 120 1991 pp 150 153 , 13 F Ellinger R Vogt and W B chtold Compact.

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